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ALC662-GR
5.1 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET
Rev. 1.0 15 January 2007 Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw
ALC662 Datasheet
COPYRIGHT (c)2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, www..com but not limited to, the particular purpose. Realtek may make improvements and/or changes in including, this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer's general information on the Realtek ALC662 Audio Codec IC. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY
Revision 1.0 Release Date 2007/01/15 Summary First release.
5.1 Channel High Definition Audio Codec
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Table of Contents
1. 2. General Description .................................................................................................... 1 Features ........................................................................................................................ 1
2.1. 2.2. HARDWARE FEATURES.....................................................................................................................1 SOFTWARE FEATURES ......................................................................................................................2
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3. 4. 5. 6.
System Applications .................................................................................................... 2 Block Diagram ............................................................................................................. 3 Pin Assignments........................................................................................................... 4
5.1.
PACKAGE AND VERSION IDENTIFICATION ........................................................................................4
Pin Descriptions........................................................................................................... 5
6.1. 6.2. 6.3. 6.4. 6.5. DIGITAL I/O PINS .............................................................................................................................5 ANALOG I/O PINS.............................................................................................................................5 FILTER/REFERENCE ..........................................................................................................................6 POWER/GROUND ..............................................................................................................................6 NC (NOT CONNECTED) PINS ............................................................................................................6
7.
High Definition Audio Link Protocol ........................................................................ 7
7.1.
7.1.1. 7.1.2.
LINK SIGNALS ..................................................................................................................................7
Signal Definitions ...................................................................................................................................................8 Signaling Topology .................................................................................................................................................9
7.2.
7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.2.5.
FRAME COMPOSITION.....................................................................................................................10
Outbound Frame - Single SDO............................................................................................................................10 Outbound Frame - Multiple SDOs....................................................................................................................... 11 Inbound Frame - Single SDI ................................................................................................................................12 Inbound Frame - Multiple SDIs...........................................................................................................................13 Variable Sample Rates..........................................................................................................................................13
7.3.
7.3.1. 7.3.2. 7.3.3.
RESET AND INITIALIZATION............................................................................................................15
Link Reset .............................................................................................................................................................15 Codec Reset ..........................................................................................................................................................16 Codec Initialization Sequence ..............................................................................................................................17 iii Rev. 1.0
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ALC662 Datasheet
7.4.
7.4.1. 7.4.2.
VERB AND RESPONSE FORMAT.......................................................................................................18
Command Verb Format ........................................................................................................................................18 Response Format..................................................................................................................................................20
7.5.
POWER MANAGEMENT ...................................................................................................................21
8.
Supported Verbs and Parameters............................................................................ 22
8.1.
8.1.1.
VERB - GET PARAMETERS (VERB ID=F00H) .................................................................................22
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h).............................................................................22 Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) ..........................................................................22 Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)......................................................23 Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) ...........................................................23 Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)................................................24 Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ...................................................24 Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah).................................................25 Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)..................................................26 Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................27 Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)................................27 Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)..............................28 Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ............................................................28 Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh).......................................................29 Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) .......................................................29 Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ...............................................................29 Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ...................................................30
8.1.2. www..com 8.1.3. 8.1.4. 8.1.5. 8.1.6. 8.1.7. 8.1.8. 8.1.9. 8.1.10. 8.1.11. 8.1.12. 8.1.13. 8.1.14. 8.1.15. 8.1.16.
8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. 8.10. 8.11. 8.12. 8.13. 8.14.
VERB - GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................30 VERB - SET CONNECTION SELECT (VERB ID=701H) .....................................................................31 VERB - GET CONNECTION LIST ENTRY (VERB ID=F02H)..............................................................31 VERB - GET PROCESSING STATE (VERB ID=F03H)........................................................................35 VERB - SET PROCESSING STATE (VERB ID=703H) ........................................................................35 VERB - GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................36 VERB - SET COEFFICIENT INDEX (VERB ID=5H)............................................................................36 VERB - GET PROCESSING COEFFICIENT (VERB ID=CH).................................................................37 VERB - SET PROCESSING COEFFICIENT (VERB ID=4H) ..................................................................37 VERB - GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................37 VERB - SET AMPLIFIER GAIN (VERB ID=3H).................................................................................40 VERB - GET CONVERTER FORMAT (VERB ID=AH)........................................................................41 VERB - SET CONVERTER FORMAT (VERB ID=2H) .........................................................................42
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8.15. VERB - GET POWER STATE (VERB ID=F05H)................................................................................43 8.16. VERB - SET POWER STATE (VERB ID=705H).................................................................................44 8.17. VERB - GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................44 8.18. VERB - SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ....................................................45 8.19. VERB - GET PIN WIDGET CONTROL (VERB ID=F07H)...................................................................46 8.20. VERB - SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................47 8.21. VERB - GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................48 8.22. VERB - SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................48 www..comVERB - GET PIN SENSE (VERB ID=F09H) ......................................................................................49 8.23. 8.24. VERB - EXECUTE PIN SENSE (VERB ID=709H) ..............................................................................49 8.25. VERB - GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH).............................50 8.26. VERB - SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3).............................................................................................................................50 8.27. VERB - GET BEEP GENERATOR (VERB ID=F0AH) .......................................................................51 8.28. VERB - SET BEEP GENERATOR (VERB ID=70AH) ........................................................................51 8.29. VERB - GET GPIO DATA (VERB ID= F15H) ..................................................................................52 8.30. VERB - SET GPIO DATA (VERB ID= 715H) ...................................................................................52 8.31. VERB - GET GPIO ENABLE MASK (VERB ID=F16H).....................................................................53 8.32. VERB - SET GPIO ENABLE MASK (VERB ID=716H)......................................................................53 8.33. VERB - GET GPIO DIRECTION (VERB ID=F17H)...........................................................................54 8.34. VERB - SET GPIO DIRECTION (VERB ID=717H)............................................................................54 8.35. VERB - GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ...........................55 8.36. VERB - SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ............................55 8.37. VERB - GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) ..............56 8.38. VERB - SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ................57 8.39. VERB - GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ......................................58 8.40. VERB - SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0]) ..................................................................................................................58 8.41. VERB - GET/SET EAPD CONTROL (VERB ID=F0CH FOR GET, 70CH FOR SET).............................59 8.42. VERB - FUNCTION RESET (VERB ID=7FFH) ..................................................................................60
9.
Electrical Characteristics ......................................................................................... 61
9.1.
9.1.1. 9.1.2. 9.1.3.
DC CHARACTERISTICS ...................................................................................................................61
Absolute Maximum Ratings ..................................................................................................................................61 Threshold Voltage .................................................................................................................................................61 S/PDIF Output Characteristics ............................................................................................................................62 v Rev. 1.0
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9.2.
9.2.1. 9.2.2. 9.2.3. 9.2.4.
AC CHARACTERISTICS ...................................................................................................................62
Link Reset and Initialization Timing.....................................................................................................................62 Link Timing Parameters at the Codec ..................................................................................................................63 S/PDIF Output Timing..........................................................................................................................................64 Test Mode..............................................................................................................................................................64
9.3.
ANALOG PERFORMANCE ................................................................................................................65
10. Application Circuits .................................................................................................. 66
10.1. www..comFILTER CONNECTION......................................................................................................................66 10.2. ONBOARD FRONT PANEL HEADER CONNECTION AND FRONT PANEL I/O ......................................67 10.3. ANALOG INPUT/OUTPUT CONNECTION ..........................................................................................68 10.4. OPTIONAL S/PDIF OUTPUT............................................................................................................68
11. Mechanical Dimensions ............................................................................................ 69
11.1. MECHANICAL DIMENSIONS NOTES.................................................................................................70
12. Ordering Information ............................................................................................... 71
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. www..com Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Digital I/O Pins ...........................................................................................................................5 Analog I/O Pins...........................................................................................................................5 Filter/Reference...........................................................................................................................6 Power/Ground .............................................................................................................................6 Not Connected Pins.....................................................................................................................6 Link RESET#..............................................................................................................................8 HDA Signal Definitions..............................................................................................................8 Defined Sample Rate and Transmission Rate...........................................................................14 48kHz Variable Rate of Delivery Timing .................................................................................14 44.1kHz Variable Rate of Delivery Timing ..............................................................................14 40-Bit Commands in 4-Bit Verb Format...................................................................................18 40-Bit Commands in 12-Bit Verb Format.................................................................................18 Supported Commands...............................................................................................................19 Supported Parameters ...............................................................................................................20 Solicited Response Format .......................................................................................................20 Unsolicited Response Format ...................................................................................................20 System Power State Definitions ...............................................................................................21 Power Controls in NID 01h ......................................................................................................21 Powered Down Conditions .......................................................................................................21 Verb - Get Parameters (Verb ID=F00h) ...................................................................................22 Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h) ...................................................22 Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) ................................................22 Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)............................23 Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) .................................23 Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h).......................24 Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) .........................24 Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ......................25 Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) ........................26 Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)..........................................27 Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) .....27 Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ...28 Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) ..................................28 Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .............................29
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Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. www..com Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) ..............................29 Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) ......................................29 Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) .........................30 Verb - Get Connection Select Control (Verb ID=F01h)...........................................................30 Verb - Set Connection Select (Verb ID=701h) .........................................................................31 Verb - Get Connection List Entry (Verb ID=F02h)..................................................................31 Verb - Get Processing State (Verb ID=F03h) ...........................................................................35 Verb - Set Processing State (Verb ID=703h)............................................................................35 Verb - Get Coefficient Index (Verb ID=Dh).............................................................................36 Verb - Set Coefficient Index (Verb ID=5h) ..............................................................................36 Verb - Get Processing Coefficient (Verb ID=Ch).....................................................................37 Verb - Set Processing Coefficient (Verb ID=4h)......................................................................37 Verb - Get Amplifier Gain (Verb ID=Bh) ................................................................................37 Verb - Set Amplifier Gain (Verb ID=3h)..................................................................................40 Verb - Get Converter Format (Verb ID=Ah) ............................................................................41 Get Converter Format Support..................................................................................................41 Verb - Set Converter Format (Verb ID=2h)..............................................................................42 Verb - Get Power State (Verb ID=F05h) ..................................................................................43 Verb - Set Power State (Verb ID=705h) ...................................................................................44 Verb - Get Converter Stream, Channel (Verb ID=F06h)..........................................................44 Verb - Set Converter Stream, Channel (Verb ID=706h)...........................................................45 Verb - Get Pin Widget Control (Verb ID=F07h) ......................................................................46 Verb - Set Pin Widget Control (Verb ID=707h) .......................................................................47 Verb - Get Unsolicited Response Control (Verb ID=F08h) .....................................................48 Verb - Set Unsolicited Response Control (Verb ID=708h) ......................................................48 Verb - Get Pin Sense (Verb ID=F09h)......................................................................................49 Verb - Execute Pin Sense (Verb ID=709h)...............................................................................49 Verb - Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)....................................50 Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) ............................................................50 Verb - Get BEEP Generator (Verb ID= F0Ah).........................................................................51 Verb - Set BEEP Generator (Verb ID= 70Ah)..........................................................................51 Verb - Get GPIO Data (Verb ID= F15h) ..................................................................................52 Verb - Set GPIO Data (Verb ID= 715h) ...................................................................................52 Verb - Get GPIO Enable Mask (Verb ID= F16h) .....................................................................53
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Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. www..com Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Verb - Set GPIO Enable Mask (Verb ID=716h).......................................................................53 Verb - Get GPIO Direction (Verb ID=F17h)............................................................................54 Verb - Set GPIO Direction (Verb ID=717h).............................................................................54 Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) ..................................55 Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) ...................................55 Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) ........................56 Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) ..........................57 Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) ........................................58 Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])...............................................................................................................58 Verb - Get EAPD Control (Verb ID=F0Ch) .............................................................................59 Verb - Set EAPD Control (Verb ID=70Ch)..............................................................................59 Verb - Function Reset (Verb ID=7FFh)....................................................................................60 Absolute Maximum Ratings .....................................................................................................61 Threshold Voltage .....................................................................................................................61 S/PDIF Output Characteristics..................................................................................................62 Link Reset and Initialization Timing ........................................................................................62 Link Timing Parameters at the Codec.......................................................................................63 S/PDIF Output Timing..............................................................................................................64 Analog Performance .................................................................................................................65 Ordering Information ................................................................................................................71
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. www..com Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Block Diagram ..........................................................................................................................3 Pin Assignments ........................................................................................................................4 HDA Link Protocol ...................................................................................................................7 Bit Timing .................................................................................................................................8 Signaling Topology ...................................................................................................................9 SDO Outbound Frame.............................................................................................................10 SDO Stream Tag is Indicated in SYNC ..................................................................................10 Striped Stream on Multiple SDOs...........................................................................................11 SDI Inbound Stream................................................................................................................12 SDI Stream Tag and Data ........................................................................................................12 Codec Transmits Data Over Multiple SDIs.............................................................................13 Link Reset Timing...................................................................................................................16 Codec Initialization Sequence.................................................................................................17 Link Reset and Initialization Timing.......................................................................................62 Link Signal Timing..................................................................................................................63 Output Timing .........................................................................................................................64 Filter Connection.....................................................................................................................66 Onboard Front Panel Header Connection and Front Panel I/O...............................................67 Analog Input/Output Connection ............................................................................................68 Optional S/PDIF Output..........................................................................................................68
5.1 Channel High Definition Audio Codec
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ALC662 Datasheet
1.
General Description
The ALC662 is a 5.1 Channel High Definition Audio Codec designed for Windows Vista desktop and mobile PCs. Its performance and functionality meet Microsoft Windows Vista (WLP 3.08) premium requirements. The ALC662 features three stereo DACs, two stereo ADCs, and legacy analog input to analog output mixing, to provide a fully-integrated audio solution for multimedia PC systems. All analog IO (except CD-IN and PCBEEP) are input and output capable, and three headphone amplifiers are also integrated to drive earphones on front (port-E and port-F) and rear panel (port-D). The ALC662 www..com supports 16/20/24-bit S/PDIF output function and a sampling rate of up to 96kHz. It offers easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers The ALC662 supports host/soft audio from the Intel ICH series chipset, and also from any other HDA compatible audio controller. With EAX/Direct Sound 3D/I3DL2/A3D compatibility, and excellent software utilities like Karaoke mode, environment emulation, software equalizer, HRTF 3D positional audio, and optional Dolby(R) Digital Live, DTS(R) CONNECTTM, and Dolby(R) Home Theater programs, ALC662 provides an excellent home entertainment package and game experience for PC users.
2.
Features
Meets performance requirements for Microsoft WLP 3.08 Vista premium and mobile PCs Six channel DAC supports 16/20/24-bit PCM format for 5.1 channel audio solution Two stereo ADC support 16/20-bit PCM format All DAC support independent 44.1k/48k/96kHz sample rate All ADC support independent 44.1k/48k/96kHz sample rate Supports 44.1k/48k/96kHz S/PDIF output All analog jack port are stereo input and output re-tasking Analog differential CD input Supports analog PCBEEP input Integrates digital BEEP generator Up to four channels of microphone array input are supported for AEC/BF application Supports legacy analog input to analog output mixer Built-in three headphone amplifiers for port-D (rear panel), port-E and port-F (front panel) Software selectable 2.5V and 3.2V reference output for microphone bias Software selectable boost gain (+10/+20/+30dB) for analog microphone input Two jack detection pins: each supports detection of up to 4 jacks
2.1. Hardware Features
5.1 Channel High Definition Audio Codec
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ALC662 Datasheet
Jack detection function is supported when device is in power down mode (D3) Supports two GPIO pins (general purpose input and output) Supports EAPD (external amplifier power down) control for external amplifier Support 1.5V~3.3V scalable I/O for HD Audio link Supports anti-pop mode when analog power AVDD is on and digital power is off 48-pin LQFP `Green' package Pin-to-pin compatible with ALC88x series, ALC660 series and ALC26x series audio codecs.
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2.2. Software Features
Compatible with Windows Vista Premium (complies with Microsoft WLP 3.08 specifications) WaveRT-based audio function driver and logo ready for Windows Vista EAXTM 1.0 & 2.0 compatible Direct Sound 3DTM compatible A3DTM compatible I3DL2 compatible HRTF 3D Positional Audio Friendly user interface for 2-foot or 10-foot remote control applications Emulation of 26 sound environments to enhance gaming experience 10 Software Equalizer Bands Voice Cancellation and Key Shifting in Karaoke mode Windows Vista style configuration panel to improve user experience Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application Features Dolby(R) Digital Live and DTS(R) CONNECTTM software (Optional) Features Dolby(R) Home Theater software (Optional)
3.
System Applications
Desktop and mobile multimedia PCs Information Appliances (IA)
5.1 Channel High Definition Audio Codec
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4.
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DAC PCM-3
04h SRC DAC VOL 0Eh 0Dh 0Ch
Front DAC Surr M Surr DAC CLfe M CLfe DAC
DAC PCM-2
03h SRC DAC VOL VOL I/O M M
Front M
M M M M 15h I/O 16h
CEN/LFE(Port-G) SURR(Port-A) FRONT(Port-D)
14h
DAC PCM-1
02h SRC DAC
Block Diagram
5.1 Channel High Definition Audio Codec
-34.5~ +12dB (1.5dB/Step)
Sample Rate: 44.1K, 48K, 96K
VOL: -64~ 0dB (1.0dB/Step)
I/OA
HDA I/ F
BEEP Gen 0Bh
Figure 1.
Front CLfe
Boost
BEEP-IN 1Dh CD-IN 1Ch
M I/OA
Surr M
1
Block Diagram
22h
M
3
VOL: -13.5~ +33dB (1.5dB/Step) Sample Rate: 44.1K, 48K, 96K
Param eters
VOL VOL VOL VOL VOL VOL VOL VOL VOL
M M M M M M M M M
1Bh
LINE2(Port-E)
I/O
Front CLfe
Boost
LINE1(Port-C)
M I/OA
CLfe
Boost
1Ah
ADC PCM-2
09h 23h
M M M M
SRC
ADC VOL M
M M M M M M M M M
MIC2(Port-F)
M
0/10/20/30dB boost
19h
M
ADC PCM-1
SRC
ADC VOL M
I/O
18h
MIC1(Port-B)
OA :Output w/ Amplifier
08h 06h
M M M M M
S/PDIF-OUT
Sample Rate: 44.1K, 48K, 96K Digital Converter
1Eh
S/PDIF-OUT
ALC662 Datasheet
Rev. 1.0
ALC662 Datasheet
5.
Pin Assignments
FRONT-R(PORT-D-R) FRONT-L(PORT-D-L) Sense B NC MIC1-VREFO-R LINE2-VREFO MIC2-VREFO NC MIC1-VREFO-L VREF AVSS1 AVDD1 NC AVDD2 SURR-L(PORT-A-L) JDREF SURR-R(PORT-A-R) AVSS2 CENTER(PORT-G-L) LFE(PORT-G-R) NC NC EAPD SPDIFO
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48
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ALC662
LLLLLLL TXXXVV
24 23 22 21 20 19 18 17 16 15 14 13
1 2 3 4 5 6 7 8 9 10 11 12
LINE1-R(PORT-C-R) LINE1-L(PORT-C-L) MIC1-R(PORT-B-R) MIC1-L(PORT-B-L) CD-R CD-GND CD-L MIC2-R(PORT-F-R) MIC2-L(PORT-F-L) LINE2-R(PORT-E-R) LINE2-L(PORT-E-L) Sense A
5.1. Package and Version Identification
Green package is indicated by a `G' in the location marked `T' in Figure 2. The version number is shown in the location marked `VV'.
5.1 Channel High Definition Audio Codec
DVDD GPIO0 GPIO1 DVSS SDATA-OUT BCLK DVSS SDATA-IN DVDD-IO SYNC RESET# PCBEEP
Figure 2.
Pin Assignments
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ALC662 Datasheet
6.
Pin Descriptions
Table 1. Digital I/O Pins Description Characteristic Definition H/W reset Vt=0.5*DVDDIO Sample Sync (48kHz) Vt=0.5*DVDDIO 24MHz Bit clock input Vt=0.5*DVDDIO Serial TDM data input Vt=0.5*DVDDIO Serial TDM data output In: Vt=0.5*DVDDIO; Out: VOH=DVDDIO, VOL=DVSS S/PDIF output TTL output has 12mA@75 driving capability External amplifier power down VOH=DVDDIO, VOL=DVSS General purpose input/output 0 In: Vt=0.5*DVDD; Out: VOH=DVDD, VOL=DVSS General purpose input/output 1 In: Vt=0.5*DVDD; Out: VOH=DVDD, VOL=DVSS Total: 9 Pins
6.1. Digital I/O Pins
Name RESET# SYNC BCLK SDATA-OUT SDATA-IN www..com SPDIFO EAPD GPIO0 GPIO1 Type I I I I O O O IO IO Pin 11 10 6 5 8 48 47 2 3
6.2. Analog I/O Pins
Name LINE2-L LINE2-R MIC2-L MIC2-R CD-L CD-GND CD-R MIC1-L MIC1-R LINE1-L LINE1-R PCBEEP FRONT-L FRONT-R SURR-L SURR-R CENTER LFE Sense A Sense B Type IO IO IO IO I I I IO IO IO IO I IO IO IO IO O O I I Pin 14 15 16 17 18 19 20 21 22 23 24 12 35 36 39 41 43 44 13 34 Table 2. Analog I/O Pins Description Characteristic Definition 2nd line input left channel Analog input/output. Default is input (JACK-E-L) 2nd line input right channel Analog input/output. Default is input (JACK-E-R) 2nd stereo microphone input Analog input/output. Default is input (JACK-F-L) left channel 2nd stereo microphone input Analog input/output. Default is input (JACK-F-R) right channel CD input left channel Analog input. 1.6Vrms of full scale input CD input reference ground Analog input. 1.6Vrms of full scale input CD input right channel Analog input. 1.6Vrms of full scale input 1st stereo microphone input Analog input/output. Default is input (JACK-B-L) left channel 1st stereo microphone input Analog input/output. Default is input (JACK-B-R) right channel 1st line input left channel Analog input/output. Default is input (JACK-C-L) 1st line input right channel Analog input/output. Default is input (JACK-C-R) External PCBEEP input Analog input. 1.6Vrms of full scale input Front output left channel Analog output (JACK-D-L) Front output right channel Analog output (JACK-D-R) Surround out left channel Analog output (JACK-A-L) Surround out right channel Analog output (JACK-A-R) Center output Analog output (JACK-G-L) Low Frequency output Analog output (JACK-G-R) Jack Detect pin l Jack resistor network input 1 Jack Detect pin 2 Jack resistor network input 2 Total: 20 Pins
5.1 Channel High Definition Audio Codec
5
Rev. 1.0
ALC662 Datasheet
6.3. Filter/Reference
Name VREF MIC1-VREFO-L MIC2-VREFO LINE2-VREFO MIC1-VREFO-R JDREF
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Type O O O O -
Pin 27 28 30 31 32 40
Table 3. Filter/Reference Description Characteristic Definition Reference voltage Typical 2.25V,10uf capacitor to analog ground Bias voltage for MIC1 jack 2.5V/3.2V reference voltage Bias voltage for MIC2 jack 2.5V/3.2V reference voltage Bias voltage for LINE2 jack 2.5V/3.2V reference voltage Bias voltage for MIC1 jack 2.5V/3.2V reference voltage Reference resistor for Jack 20K, 1% external resistor to analog ground detection Total: 6 Pins
6.4. Power/Ground
Name AVDD1 AVSS1 AVDD2 AVSS2 DVDD DVSS DVDD-IO DVSS Type I I I I I I I I Pin 25 26 38 42 1 4 9 7 Table 4. Description Analog VDD Analog GND Analog VDD Analog GND Digital VDD Digital GND Digital VDD Digital GND Power/Ground Characteristic Definition Analog power for mixer and amplifier Analog ground for mixer and amplifier Analog power for DACs and ADCs Analog ground for DACs and ADCs Digital power for core Digital ground for core Digital power for HDA link (1.5V~3.3V) Digital ground for HDA link Total: 8 Pins
6.5. NC (Not Connected) Pins
Symbol NC Type Table 5. Pin 29, 33, 37, 45, 46 Not Connected Pins Description Not Connected. Total: 5 Pins
5.1 Channel High Definition Audio Codec
6
Rev. 1.0
ALC662 Datasheet
7.
High Definition Audio Link Protocol
7.1. Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent by the HDA controller. The input and output streams, including command and PCM data, are isochronous with a 48kHz frame rate. Figure 3 shows the basic concept of the HDA link protocol.
Previous Frame www..com BCLK Frame SYNC= 8 BCLK SYNC Stream 'A' Tag (Here 'A' = 5) Stream 'B' Tag (Here 'B' = 6) Tframe_sync = 20.833 s (48KHz) Next Frame
SDO
Command Stream (40-bit data)
Stream 'A' Data
Stream 'B' Data
SDI
Response Stream (36-bit data)
Stream 'C' Tag
Stream 'C' Data (n bytes + 10-bit data)
RST#
Figure 3.
HDA Link Protocol
5.1 Channel High Definition Audio Codec
7
Rev. 1.0
ALC662 Datasheet
7.1.1.
Item BCLK SYNC SDO
Signal Definitions
Table 6. Link RESET# Description 24.0MHz bit clock sourced from the HDA controller and connecting to all codecs. A 48kHz signal used to synchronize input and output streams on the link. It is sourced from the HDA controller and connects to all codecs. Serial Data Output signal driven by the HDA controller to all codecs. Commands and data streams are carried on SDO. The data rate is double-pumped; the controller drives data onto the SDO, the codec samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. Serial Data Input signal driven by the codec. This is point-to-point serial data from the codec to the HDA controller. The controller must support at least one SDI. Up to a maximum of 15 SDI's can be supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of BCLK. SDI can be driven by the controller to initialize the codec's ID. Active low reset signal. Asserted to reset the codec to default power-on state. RESET# is sourced from the HDA controller and connects to all codecs.
SDI
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RESET#
Table 7. HDA Signal Definitions Signal Name Source Type for Controller Description BCLK Controller Output Global 24.0MHz bit clock. SYNC Controller Output Global 48kHz Frame Sync and outbound tag signal. SDO Controller Output Serial data output from controller. SDI Codec/Controller Input/Output Serial data input from codec. Weakly pulled down by the controller. RESET# Controller Output Global active low reset signal.
BCLK SYNC
8-Bit Frame SYNC Start of Frame
SDO SDI
7
6
5
4
3
2
1
0 999 998 997 996 995 994 993 992 991 990
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK Controller samples SDI at rising edge of BCLK
Figure 4.
Bit Timing
5.1 Channel High Definition Audio Codec
8
Rev. 1.0
ALC662 Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream. RESET#, BCLK, SYNC, SDO0, and SDO1 are driven by the controller to codecs. Each codec drives its own point-to-point SDI signal(s) to the controller. Figure 5, on page 9, shows the possible connections between the HDA controller and codecs: * * * Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission Codec 1 has two SDOs for doubled outbound rate, and a single SDI for normal inbound rate 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate Codec N has two SDOs and multiple SDIs
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The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and codecs. Section 7.2 Frame Composition, page 10, describes the detailed outbound and inbound stream compositions for single and multiple SDOs/SDIs. The connections shown in Figure 5 can be implemented concurrently in an HDA system. The ALC662 is designed to receive a single SDO stream.
SDI14 . . . SDI13 SDI2 HDA SDI1 Controller SDI0 SDO1 SDO0 SYNC BCLK RST#
. . .
5.1 Channel High Definition Audio Codec
SDO0 SYNC BCLK RST#
S DI0 SDO1 SDO0 SYNC BCLK RST#
SDI2 SDI1 SDI0 SDO1 SDO0 SYNC BCLK RST#
SDO0 SYNC BCLK RST#
SDI0
SDI1 SDI0
...
Codec 0 Single SDO Single SDI
Codec 1 Two SDOs Single SDI
Codec 2 Single SDO Two SDIs
Codec N Two SDOs Multiple SDIs
Figure 5.
Signaling Topology
9
Rev. 1.0
ALC662 Datasheet
7.2. Frame Composition
7.2.1. Outbound Frame - Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry 96kHz samples (Figure 6).
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For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 7). To keep the cadence of converters bound to the same stream, samples for these converters must be placed in the same block.
Previous Frame
A 48kHz Frame is composed of Command stream and multiple Data streams Stream 'A' Tag (Here 'A' = 5) Stream 'X' Tag (Here 'X' = 6)
Next Frame
Frame SYNC
SYNC
SDO
Command Stream
Stream 'A' Data
Stream 'X' Data
0s
Sample Block(s) Block 1 Sample 1 Block 2 Sample 2 ... lsb .. . .. .
One or multiple blocks in a stream
Null Field
Padded at the end of Frame
Block Y
For 48kHz rate, only Block1 is included For 96kHz rate, Block1 includes (N)th time of samples, Block2 includes (N+1)th time of samples
Sample Z Z channels of PCM sample
msb
msb first in a sample
Figure 6.
SDO Outbound Frame
BCLK
Stream Tag
msb SYNC
Preamble (4-Bit)
lsb
1010
Stream=10 (4-Bit) ms b Data of Stream 10
SDO
76543210 Previous Stream
Figure 7. 5.1 Channel High Definition Audio Codec
SDO Stream Tag is Indicated in SYNC 10 Rev. 1.0
ALC662 Datasheet
7.2.2.
Outbound Frame - Multiple SDOs
The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission in less time to get more bandwidth. If software determines that the target codec supports multiple SDO capability, it enables the `Stripe Control' bit in the controller's Output Stream Control Register to initiate a specific stream (Stream `A' in Figure 8) to be transmitted on multiple SDOs. In this case, the MSB of stream data is always carried on SDO0, the second bit on SDO1 and so forth. SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to SDO0.
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that all codecs can determine their corresponding stream, the command stream is not striped. It is always transmitted on SDO0, and copied on SDO1.
Figure 8.
Striped Stream on Multiple SDOs
5.1 Channel High Definition Audio Codec
11
Rev. 1.0
ALC662 Datasheet
7.2.3.
Inbound Frame - Single SDI
An Inbound Frame - Single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 9). The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure 10).
www..com Previous Frame
A 48kHz Frame is Composed of a Response Stream and Multiple Data streams
Next Frame
Frame SYNC SYNC
SDI
Response Stream
Stream 'A'
Stream 'X'
0s
Null Field Stream Tag Block 1 Sample Block(s) ... ... lsb Block Y Null Pad
Padded at the end of Frame
Block 2
For 48kHz rate, only Block1 is included For 96kHz rate, Block{1, 2} includes {(N) th (N+1)th} time of samples
Sample 1 Sample 2 msb ...
Sample Z Z channels of PCM sample
msb first in a sample
Figure 9.
SDI Inbound Stream
BCLK
Stream Tag Data Length in Bytes B6 B5 B4 B3 B2 B1
n-Bit Sample Block
Null Pad 0 0 0 0
Next Stream
SDI
B9
B8
B7
B0 Dn-1 Dn-2
D0
(Data Length in Bytes *8)-Bit A Complete Stream
Figure 10. SDI Stream Tag and Data
5.1 Channel High Definition Audio Codec
12
Rev. 1.0
ALC662 Datasheet
7.2.4.
Inbound Frame - Multiple SDIs
A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth. If an inbound stream exceeds the data transfer limits of a single SDI, the codec can divide the data onto separate SDI signals, each of which operate independently, with different stream numbers at the same frame time. This is similar to having multiple codecs connected to the controller. The controller samples the divided stream into separate memory with multiple DMA descriptors, then software re-combines the divided data into a meaningful stream.
SYNC Frame SYNC www..com SDI 0 Response Stream Stream 'A' Tag A Data A Stream 'B' SDI 1 Response Stream Tag B Data B 0s 0s Stream 'X' Stream 'Y'
Codec drives SDI0 and SDI1
Stream A, B, X, and Y are independent and have separate IDs
Figure 11. Codec Transmits Data Over Multiple SDIs
7.2.5.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable sample rates are delivered in multiple or sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate, one sample block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own sample rate, independent of any other stream. The HDA controller supports 48kHz and 44.1kHz base rates. Table 8, page 14, shows the recommended sample rates based on multiples or sub-multiples of one of the two base rates. Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in multiples (n) of 48kHz contain n sample blocks in a frame. Table 9, page 14, shows the delivery cadence of variable rates based on 48kHz. The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample blocks are transmitted every 160 frames. The cadence "12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)" interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame AND interleave an empty frame between non-empty frames (Table 10, page 14).
5.1 Channel High Definition Audio Codec 13 Rev. 1.0
ALC662 Datasheet
(Sub) Multiple 1/6 1/4 1/3 1/2 2/3 1 2 4 Table 8. Defined Sample Rate and Transmission Rate 48kHz Base 44.1kHz Base 8kHz (1 sample block every 6 frames) 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames) 16kHz (1 sample block every 3 frames) 22.05kHz (1 sample block every 2 frames) 32kHz (2 sample blocks every 3 frames) 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame) 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame) 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)
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Table 9. Rate Delivery Cadence 8kHz YNNNNN (repeat) 12kHz YNNN (repeat) 16kHz YNN (repeat) 32kHz Y2NN (repeat) 48kHz Y (repeat) 96kHz Y2 (repeat) 192kHz Y4 (repeat) N: No sample block in a frame Y: One sample block in a frame Yx: X sample blocks in a frame
48kHz Variable Rate of Delivery Timing Description One sample block is transmitted in every 6 frames One sample block is transmitted in every 4 frames One sample block is transmitted in every 3 frames One sample block is transmitted in every 6 frames One sample block is transmitted in every 6 frames Two sample blocks are transmitted in each frame Four sample blocks are transmitted in each frame
Table 10. 44.1kHz Variable Rate of Delivery Timing Rate Delivery Cadence 11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat) 88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat) 174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN {11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN { - }=NNNN 22.050kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN {11}=YNYNYNYNYNYNYNYNYNYNYN { - }=NN
5.1 Channel High Definition Audio Codec
14
Rev. 1.0
ALC662 Datasheet
44.1kHz 88.2kHz 174.4kHz 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no sample block. 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block. 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block.
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7.3. Reset and Initialization
There are two types of reset within an HDA link: * * Link Reset. Generated by assertion of the RESET# signal. All codecs return to their power-on state Codec Reset. Generated by software directing a command to reset a specific codec back to its default state
An initialization sequence is requested after any of the following three events: * * * Link Reset Codec Reset Codec changes its power state, e.g., hot docking a codec to an HDA system
7.3.1.
1. 2. 3.
Link Reset
A link reset may be caused by any of the following three events: The HDA controller asserts RESET# for any reason (power up, or PCI reset) Software initiates a link reset via the `CRST' bit in the Global Control Register (GCR) of the HDA controller Software initiates power management sequences. Figure 12, page 16, shows the `Link Reset' timing including the `Enter' sequence ( ~ ) and `Exit' sequence ( ~ )
Enter `Link Reset': Software writes a 0 to the `CRST' bit in the Global Control Register of the HDA controller to initiate a link reset As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame
5.1 Channel High Definition Audio Codec 15 Rev. 1.0
ALC662 Datasheet
The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low The controller asserts the RESET# signal to low, and enters the `Link Reset' state All link signals driven by controller and codecs should be tri-state by internal pull-low resistors
Exit from `Link Reset': If BCLK is re-started for any reason (codec, wake-up event, power management, etc.)
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Software is responsible for de-asserting RESET# after a minimum of 100s BCLK running time (the 100sec provides time for the codec PLL to stabilize) Minimum of 4 BCLKs after RESET# is de-asserted, the controller starts to signal normal frame SYNC
The codec drives its SDI to request an initialization sequence (when the SDI is driven high at the last bit of frame SYNC)
Previous Frame 4 BCLK 4 BCLK Link in Reset >=100 usec >= 4 BCLK Initialization Sequence
BCLK SYNC
2 Normal Frame SYNC is absent Driven Low Normal Frame SYNC 8 Driven Low Pulled Low Wake Event 9
Pulled Low
SDOs SDIs RST#
1 3
Driven Low
Pulled Low
Pulled Low 4 5 6 7
Figure 12. Link Reset Timing
7.3.2.
Codec Reset
A `Codec Reset' is initiated via the Codec RESET command verb. It results in the target codec being reset to the default state. After the target codec completes its reset operation, an initialization sequence is requested.
5.1 Channel High Definition Audio Codec
16
Rev. 1.0
ALC662 Datasheet
7.3.3.
Codec Initialization Sequence
The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the controller The codec stops driving the SDI during this turnaround period The controller drives SDI to assign a CAD to the codec The controller releases the SDI after the CAD has been assigned Normal www..com operating state
Connection Frame Turnaround Frame (Non-48kHz Frame) Address Frame (Non-48kHz Frame) Normal Operation
Exit from Reset
BCLK SYNC SDIx RST#
1 2 3
Frame SYNC
Frame SYNC
4 5 6 SD14 7 8
Frame SYNC Response
SD0 SD1
Codec Drives SDIx
Codec Turnaround (477 BCLK Max.)
Controller Drives SDIx
Controller Turnaround (477 BCLK Max.)
Codec Drives SDIx
Figure 13. Codec Initialization Sequence
5.1 Channel High Definition Audio Codec
17
Rev. 1.0
ALC662 Datasheet
7.4. Verb and Response Format
7.4.1. Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 11 shows the 4-bit verb structure of a command stream sent from the controller to operate the codec. Table 12 is the 12-bit verb structure that gets and controls parameters in the codec.
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Bit [39:32] Reserved
Table 11. 40-Bit Commands in 4-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:16] Codec Address Node ID Verb ID
Bit [15:0] Payload
Bit [39:32] Reserved
Table 12. 40-Bit Commands in 12-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:8] Codec Address Node ID Verb ID
Bit [7:0] Payload
5.1 Channel High Definition Audio Codec
18
Rev. 1.0
ALC662 Datasheet
Table 13. Supported Commands Modem Function Group*1 HDMI Function Group*1 Vendor Define Group*1 Audio Function Group Vendor Define Widget Y Y Y Rev. 1.0 Audio Out Converter Audio In Converter
Get parameter www..com
F00 Y Y Y Y Y Y Connection Select F01 701 Y Y Get Connection List Entry F02 Y Y Y Processing State F03 703 Coefficient Index D-- 5-Processing Coefficient C-- 4-Amplifier Gain/Mute B-- 3-Y Y Y Stream Format A-- 2-Y Y Digital Converter 1 F0D 70D Y Y Digital Converter 2 F0D 70E Y Y Power State F05 705 Y Channel / Stream ID F06 706 Y Y SDI Select F04 704 Pin Widget Control F07 707 Y Unsolicited Enable F08 708 Y Pin Sense F09 709 Y EAPD / BTL Enable F0C 70C All GPIO Control F10- 710F1A 71A Beep Generator Control F0A 70A Volume Knob Control F0F 70F Subsystem ID, Byte 0 F20 720 Y Subsystem ID, Byte 1 F20 721 Y Subsystem ID, Byte 2 F20 722 Y Subsystem ID, Byte 3 F20 723 Y Config Default, Byte 0 F1C 71C Y Config Default, Byte 1 F1C 71D Y Config Default, Byte 2 F1C 71E Y Config Default, Byte 3 F1C 71F Y RESET 7FF Y *1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.
Set Verb
Supported Verb
Y Y Y
Y
Y
Y
5.1 Channel High Definition Audio Codec
19
Beep Generator Y Y
Selector Widget
Power Widget*1
Volume Knob
Sum Widget
Pin Widget
Root Node
Get Verb
ALC662 Datasheet
Table 14. Supported Parameters Modem Function Group*1 HDMI Function Group*1 Vendor Define Group*1 Audio Function Group Vendor Define Widget Y Y Y Rev. 1.0 Audio Out Converter
Audio In Converter
Supported Parameter
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00 Y Revision ID 02 Y Subordinate Node Count 04 Y Y Function Group Type 05 Y Audio Function Group 08 Y Capabilities Audio Widget Capabilities 09 Y Y Y Sample Size, Rate 0A Y Y Y Stream Formats 0B Y Y Y Pin Capabilities 0C Y Input Amp Capabilities 0D Y Output Amp Capabilities 12 Y Connection List Length 0E Y Y Supported Power States 0F Y Y Y Y Processing Capabilities 10 GPI/O Count 11 Volume Knob Capabilities 13 *1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.
Y
Y
Y
Y
Y Y Y Y
Y Y Y
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the codec in response to a current command verb. The codec will send Solicited Response data in the next frame, without regard to the Set (Write) or Get (Read) command. The 32-bit response is interpreted by software, opaque to the controller. Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI status information can be actively delivered to the controller and interpreted by software. The `Tag' in Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Bit [35] Valid Table 15. Solicited Response Format Bit [34] Bit [33:32] Unsol=0 Reserved Bit [31:0] Response
Bit [35] Valid
Table 16. Unsolicited Response Format Bit [34] Bit [33:32] Bit [31:28] Unsol=1 Reserved Tag 20
Bit [27:0] Response
5.1 Channel High Definition Audio Codec
Beep Generator Y
Selector Widget
Power Widget*1
Parameter ID
Volume Knob
Sum Widget
Pin Widget
Root Node
ALC662 Datasheet
7.5. Power Management
The ALC662 does not support Wake-Up events when in low-power mode. All power management state changes in widgets are driven by software. Table 17 shows the System Power State Definitions. Table 18 indicates those nodes that support power management. To simplify power control, software can configure whole codec power states through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no individual power control to supply fine-grained power control.
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Power States D0 D1 D2 D3 (Hot) D3 (Cold)
Table 17. System Power State Definitions Definitions All power on. Individual DACs and ADCs can be powered up or down as required All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog reference stays up All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog reference is off (D1 + analog reference off) Power still supplied. The codec stops the internal clock. State is maintained All power removed. State lost Power Controls in NID 01h D0 D1 D2 Normal Normal Normal Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal PD PD Normal Normal PD Normal Normal PD Normal Normal PD
Table 18. Item Description Audio Function LINK Response (NID=01h) Front DAC (Node 02h) Surr DAC (Node 03h) Cen/LFE DAC (Node 04h) ADC (Node 08h) ADC (Node 09h) All Headphone Drivers All Mixers All Reference Note: PD=Powered Down
D3 PD PD PD PD PD PD PD PD PD
Link Reset PD PD PD PD PD PD Normal Normal Normal
Condition LINK Response powered down
Front DAC powered down Surr DAC powered down CEN/LFE DAC powered down ADC 08h powered down ADC 09h powered down Headphone Driver powered down Mixers powered down Reference power down
Table 19. Powered Down Conditions Description Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of `Link Reset Entry' and `Link Reset Exit' sequences are supported. All states are maintained if DVDD is supplied Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down Analog block and digital filter are powered down. Data on SDATA-IN is quiet Analog block and digital filter are powered down. Data on SDATA-IN is quiet All headphone drivers are powered down All internal mixer widgets are powered down. The DC reference and VREFOUTx at individual pin complexes are still alive All internal references, DC reference, and VREFOUTx at individual pin complexes are off 21 Rev. 1.0
5.1 Channel High Definition Audio Codec
ALC662 Datasheet
8.
Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC662. If a verb is not supported by the addressed widget, it will respond with 32 bits of `0'.
8.1. Verb - Get Parameters (Verb ID=F00h)
The `Get Parameters' verb is used to get system information and the function capabilities of the HDA codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget. Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format, www..com page 18, to get detailed information about supported parameters.
Table 20. Verb - Get Parameters (Verb ID=F00h) Get Parameter Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response Note: If the parameter ID is not supported, the returned response is 32 bits of `0'.
8.1.1.
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 21. Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h) Codec Response Format Bit Description 31:16 Vendor ID=10ECh (Realtek's PCI vendor ID) 15:0 Device ID=0662h Note 1: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 22. Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's 23:20 MajRev=1h. The major version number (in decimal) of the HDA Specification 19:16 MinRev=0h. The minor version number (in decimal) of the HDA Specification 15:8 Revision ID. The vendor's revision number Note: 01h indicates ALC662 silicon. 7:0 Stepping ID. The vendor's stepping number within the given Revision ID Note: The Root Node (NID=00h) supports this parameter.
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8.1.3.
Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node.
Table 23. Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Codec Response Format Bit Description www..com 31:24 Reserved. Read as 0's 23:16 Starting Node Number The starting node number in the sequential widgets 15:8 Reserved. Read as 0's. 7:0 Total Number of Nodes For a root node, this is the total number of function groups in the root node For a function group, this is the total number of widget nodes in the function group
8.1.4.
Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h)
Table 24. Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) Codec Response Format Bit Description 31:9 Reserved. Read as 0's 8 UnSol Capable 0: Unsolicited response is not supported by this function group 1: Unsolicited response is supported by this function group 7:0 Function Group Type 00h: Reserved 01h: Audio Function 02h: Modem Function 03h~7Fh: Reserved 80h~FFh: Vendor Defined Function
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8.1.5.
Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Table 25. Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) Codec Response Format Bit Description 31:17 Reserved. Read as 0's 16 Beep Generator A `1' indicates the presence of an integrated Beep generator within the Audio Function Group 15:12 Reserved. Read as 0's 11:8 Input Delay Number of samples delay from analog input to HDA link www..com 7:4 Reserved. Read as 0's 3:0 Output Delay Number of samples delay from HDA link to analog output
8.1.6.
Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Table 26. Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's 23:20 Widget Type 0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex 5h: Power Widget 6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget 19:16 Delay. Samples delayed between the HDA link and widgets 15:12 Reserved. Read as 0's 11: L-R Swap 0: Left channel and right channel swapping is not supported 1: Left channel and right channel swapping is supported 10 Power Control 0: Power control is not supported on this widget 1: Power control is supported on this widget 9 Digital 0: An analog input or output converter 1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.) 8 ConnList. Connection List 0: Connected to HDA link. No Connection List Entry will be queried 1: Connection List Entry must be queried 7 UnsolCap. Unsolicited Capable 0: Unsolicited response is not supported 1: Unsolicited response is supported 6 ProcWidget. Processing Widget 0: No processing control 1: Processing control is supported 5 Reserved. Read as 0 4 Format Override Note: The ALC662 supports 16/20/24-bit with 44.1kHz, 48kHz, and 96kHz sample rate. The format (parameter ID=0Ah) must be queried
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Codec Response Format Bit Description 3 AmpParOvr (AMP Param Override) Override amplifier parameters (Gain Control) in individual output Pin Complexes, ADCs, and Mixer widgets 2 OutAmpPre (Out AMP Present) 1 InAmpPre (In AMP Present) There are amplifiers (Gain Control) in individual ADCs and Mixer widgets 0 Stereo 0: Mono Widget 1: Stereo Widget
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8.1.7.
Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Parameters in audio functions provide default information about formats. Individual converters have their own parameters to provide supported formats if their `Format Override' bit is set.
Table 27. Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) Codec Response Format Bit Description 31:21 Reserved. Read as 0's 20 B32. 32-bit audio format support 0: Not supported 1: Supported 19 B24. 24-bit audio format support 0: Not supported 1: Supported (The ALC662 DAC supports this format) 18 B20. 20-bit audio format support 0: Not supported 1: Supported (The ALC662 DAC supports this format) 17 B16. 16-bit audio format support 0: Not supported 1: Supported (The ALC662 DAC supports this format) 16 B8. 8-bit audio format support 0: Not supported 1: Supported 15:12 Reserved. Read as 0's 11 R12. 384kHz (=8*48kHz) rate support 0: Not supported 1: Supported 10 R11. 192kHz (=4*48kHz) rate support 0: Not supported 1: Supported 9 R10. 176.4Hz (=4*44.1kHz) rate support 0: Not supported 1: Supported 8 R9. 96kHz (=2*48kHz) rate support 0: Not supported 1: Supported (The ALC662 DAC and ADC support this sample rate)
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Codec Response Format Bit Description 7 R8. 88.2kHz (=2*44.1kHz) rate support 0: Not supported 1: Supported 6 R7. 48kHz rate support 0: Not supported 1: Supported (The ALC662 DAC and ADC support this sample rate) 5 R6. 44.1kHz rate support 0: Not supported 1: Supported (ALC662 DAC and ADC support this sample rate) 4 R5. 32kHz (=2/3*48kHz) rate support 0: Not supported www..com 1: Supported 3 R4. 22.05kHz (=1/2*44.1kHz) rate support 0: Not supported 1: Supported 2 R3. 16kHz (=1/3*48kHz) rate support 0: Not supported 1: Supported 1 R2. 11.025kHz (=1/4*44.1kHz) rate support 0: Not supported 1: Supported 0 R1. 8kHz (=1/6*48kHz) rate support 0: Not supported 1: Supported
8.1.8.
Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the `Format Override' bit is set.
Table 28. Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Codec Response Format Bit Description 31:3 Reserved. Read as 0's 2 AC3 0: Not supported 1: Supported 1 Float32 0: Not supported 1: Supported 0 PCM 0: Not supported 1: Supported (The ALC662 DAC and ADC support this format) Note: Input converters and output converters support this parameter.
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8.1.9.
Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 29. Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) Codec Response Format Bit Description 31:16 Reserved. Read as 0's 15:8 VREF Control Capability `1' in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of AVDD. 7:6 5 4 3 2 1 0 www..com Reserved 100% 80% Reserved Ground 50% Hi-Z 7 Reserved 6 Balanced I/O Pin `1' indicates this pin complex has balanced pins 5 Input Capable `1' indicates this pin complex supports input 4 Output Capable `1' indicates this pin complex supports output 3 Headphone Drive Capable `1' indicates this pin complex has an amplifier to drive a headphone 2 Presence Detect Capable `1' indicates this pin complex can detect whether there is a device plugged in 1 Trigger Required `1' indicates whether a software trigger is required for an impedance measurement 0 Impedance Sense Capable `1' indicates this pin complex can perform analog sense on the attached device to determine its type Note: Only Pin Complex widgets support this parameter.
8.1.10. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 30. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) Codec Response Format Bit Description 31 (Input) Mute Capable 30:23 Reserved. Read as 0 22:16 Step Size Indicates the size of each step in the gain range 15 Reserved. Read as 0 14:8 Number of Steps Indicates the number of steps in the gain range. `0' means the gain is fixed 7 Reserved. Read as 0 6:0 Offset Indicates which step is 0dB
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8.1.11. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 31. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) Codec Response Format Bit Description 31 (Output) Mute Capable 30:23 Reserved. Read as 0 22:16 Step Size www..com Indicates the size of each step in the gain range. Each individual step may be 0~32dB, specified in 0.25dB steps. `0' indicates 0.25dB steps. `127' indicates 32dB steps. 15 Reserved. Read as 0 14:8 Number of Steps Indicates the number of steps in the gain range. `0' means the gain is fixed 7 Reserved. Read as 0 6:0 Offset. Indicates which step is 0dB
8.1.12. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 32. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) Codec Response Format Bit Description 31:8 Reserved. Read as 0 7 Short Form 0: Short Form 1: Long Form 6:0 Connect List Length Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input, and there is no Connection Select Control (not a MUX widget)
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8.1.13. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Table 33. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Codec Response Format Bit Description 31:4 Reserved. Read as 0's 3 D3Sup 1: Power state D3 is supported 2 D2Sup 1: Power state D2 is supported 1 D1Sup www..com 1: Power state D1 is supported 0 D0Sup 1: Power state D0 is supported
8.1.14. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Table 34. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) Codec Response Format Bit Description 31:16 Reserved. Read as 0's 15:8 NumCoeff. Number of Coefficient 7:1 Reserved. Read as 0's 0 Benign 0: Processing unit is not linear and time invariant 1: Processing unit is linear and time invariant
8.1.15. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Table 35. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0 The ALC662 does not support GPIO wake-up function 30 GPIUnsol=1 The ALC662 supports GPIO unsolicited response 29:24 Reserved. Read as 0's 23:16 NumGPIs=00h No GPI pin is supported 15:8 NumGPOs=00h No GPO pin is supported 7:0 NumGPIOs=02h Two GPIO pins are supported
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8.1.16. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Table 36. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) Codec Response Format for NID=21h (Volume Control Knob) Bit Description 31:8 Reserved. Read as 0's 7 Delta 0: Software cannot modify the Volume Control Knob volume 1: Software can write a base volume to the Volume Control Knob 6:0 NumSteps The number of steps in the range of the Volume Control Knob www..com Note: The ALC662 does not support volume knob and will respond with 0s to this parameter.
8.2. Verb - Get Connection Select Control (Verb ID=F01h)
Table 37. Verb - Get Connection Select Control (Verb ID=F01h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F01h 0's Bit[7:0] are Connection Index Codec Response for NID = 19h (MIC2, PORT-F) Bit Description 31:8 0's 7:0 Connection Index currently Set (Default value is 00h) 00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Eh Other: Reserved Codec Response for NID = 1Bh (LINE2, PORT-E) Bit Description 31:8 0's 7:0 Connection Index currently Set (Default value is 00h) 00h: Sum Widget NID=0Ch 01h: Sum Widget NID=0Eh Other: Reserved Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.3. Verb - Set Connection Select (Verb ID=701h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 38. Verb - Set Connection Select (Verb ID=701h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=701h Select Index [7:0] 0's for all nodes
8.4. Verb - Get Connection List Entry (Verb ID=F02h)
Table 39. Verb - Get Connection List Entry (Verb ID=F02h) Get Command Format Codec Response Format www..com Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response
Codec Response for NID=08h (ADC) Bit Description 31:8 Connection List Entry (N+3), (N+2) and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 23h (Sum Widget) for N=0~3 Returns 00h for N>3
Codec Response for NID=09h (ADC) Bit Description 31:8 Connection List Entry (N+3), (N+2) and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 22h (Sum Widget) for N=0~3 Returns 00h for N>3
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Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3) Returns 1Bh (Pin Complex - LINE2) for N=0~3 Returns 15h (Pin Complex - SURR) for N=4~7 Returns 00h for N>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Complex - LINE1) for N=0~3 Returns 14h (Pin Complex - FRONT) for N=4~7 Returns 00h for N>7 15:8 Connection List Entry (N+1) Returns 19h (Pin Complex - MIC2) for N=0~3. Returns 1Dh (Pin Complex - PCBEEP) for N=4~7 www..com Returns 00h for N>7 7:0 Connection List Entry (N) Returns 18h (Pin Complex - MIC1) for N=0~3 Returns 1Ch (Pin Complex - CD) for N=4~7 Returns 16h (Pin Complex - CEN/LFE) for N=8~11 Returns 00h for N>11
Codec Response for NID=0Ch (Front Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 02h (Front DAC) for N=0~3 Returns 00h for N>3
Codec Response for NID=0Dh (Surround Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 03h (Surround DAC) for N=0~3. Returns 00h for N>3.
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Codec Response for NID=0Eh (Cen/Lfe Sum) Bit Description 31:24 Connection List Entry (N) Returns 00h 23:16 Connection List Entry (N+2) Returns 00h 15:8 Connection List Entry (N+1) Returns 0Bh (Mixer) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 04h (Cen/Lfe DAC) for N=0~3 Returns 00h for N>3
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Codec Response for NID=14h (FRONT, Port-D) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1) Returns 000000h for n>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 00h for N>3
Codec Response for NID=15h (SURR, Port-D) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1) Returns 000000h for n>3 7:0 Connection List Entry (N) Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>3
Codec Response for NID=16h (CEN/LFE, Port-G) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1) Returns 000000h for n>3 7:0 Connection List Entry (N) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3
Codec Response for NID=18h (MIC1, Port-B) Bit Description 31:8 Connection List Entry (N+3), (N+2), (N+1) Returns 000000h for n>3 7:0 Connection List Entry (N) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3
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Codec Response for NID=19h (MIC2, Port-F) Bit Description 31:16 Connection List Entry (N+3), (N+2) Returns 0000h for n>3 15:8 Connection List Entry (N+1) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 00h for N>3
Codec Response www..com Bit 31:8 7:0
for NID=1Ah (LINE1, Port-C) Description Connection List Entry (N+3), (N+2), (N+1) Returns 000000h for n>3 Connection List Entry (N) Returns 0Dh (Sum Widget NID=0Dh) for N=0~3 Returns 00h for N>3
Codec Response for NID=1Bh (LINE2, Port-E) Bit Description 31:16 Connection List Entry (N+3), (N+2) Returns 0000h for n>3 15:8 Connection List Entry (N+1) Returns 0Eh (Sum Widget NID=0Eh) for N=0~3 Returns 00h for N>3 7:0 Connection List Entry (N) Returns 0Ch (Sum Widget NID=0Ch) for N=0~3 Returns 00h for N>3
Codec Response for NID=1Eh (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1) Returns 000000h 7:0 Connection List Entry (N) Returns 06h (S/PDIF-OUT Converter) for N=0~3 Returns 00h for N>3
Codec Response for NID=22h/23h (Sum Widget) Bit Description 31:23 Connection List Entry (N+3) Returns 1Bh (Pin Widget LINE2, port-E) for N=0~3 Returns 15h (Pin Widget SURR, port-A) for N=4~7 Returns 00h for n>7 23:16 Connection List Entry (N+2) Returns 1Ah (Pin Widget LINE1, port-C) for N=0~3 Returns 14h (Pin Widget FRONT, port-D) for N=4~7 Returns 00h for N>7 5.1 Channel High Definition Audio Codec 34 Rev. 1.0
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Codec Response for NID=22h/23h (Sum Widget) Bit Description 15:8 Connection List Entry (N+1) Returns 19h (Pin Widget MIC2, port-F) for N=0~3 Returns 1Dh (Pin Widget PCBEEP) for N=4~7 Returns 0Bh (Mixer) for N=8~11 Returns 00h for N>11 7:0 Connection List Entry (N) Returns 18h (Pin Widget MIC1, port-B) for N=0~3 Returns 1Ch (Pin Widget CD) for N=4~7 Returns 16h (Pin Widget CEN/LFE, port-G) for N=8~11 Returns 00h for N>11
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Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.5. Verb - Get Processing State (Verb ID=F03h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 40. Verb - Get Processing State (Verb ID=F03h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F03h 0's 32-bit response
Codec Response for All NID Bit Description 31:0 Not supported (returns 00000000h)
8.6. Verb - Set Processing State (Verb ID=703h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 41. Verb - Set Processing State (Verb ID=703h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=703h Processing State [7:0] 0's for all nodes
Codec Response for all NID Bit Description 31:0 0's
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8.7. Verb - Get Coefficient Index (Verb ID=Dh)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=20h Table 42. Verb - Get Coefficient Index (Verb ID=Dh) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Dh 0's Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers) Bit Description 31:16 Reserved. Read as 0's 15:0 Coefficient Index www..com Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.8. Verb - Set Coefficient Index (Verb ID=5h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=20h Table 43. Verb - Set Coefficient Index (Verb ID=5h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=5h Coefficient Index [15:0] 0's for all nodes
Codec Response for All NID Bit Description 31:0 0's
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8.9. Verb - Get Processing Coefficient (Verb ID=Ch)
Table 44. Verb - Get Processing Coefficient (Verb ID=Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0] CAd=X Node ID=20h Verb ID=Ch 0's Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Registers) Bit Description 31:16 Reserved. Read as 0's 15:0 Processing Coefficient www..com Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h)
8.10. Verb - Set Processing Coefficient (Verb ID=4h)
Table 45. Verb - Set Processing Coefficient (Verb ID=4h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0] CAd=X Node ID=20h Verb ID=4h Coefficient [15:0] 0's for all nodes
Codec Response for All NID Bit Description 31:0 0's
8.11. Verb - Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 46. Verb - Get Amplifier Gain (Verb ID=Bh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:16] Verb ID=Bh Payload Bit [15:0] `Get' payload [15:0] Codec Response Format Response [31:0] Bit[7:0] are responsible for `Get'
`Get' Payload in Command Bit[15:0] Bit Description 15 Get Input/Output 0: Input amplifier gain is requested 1: Output amplifier gain is requested 14 Reserved. Read as 0 5.1 Channel High Definition Audio Codec 37 Rev. 1.0
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`Get' Payload in Command Bit[15:0] Bit Description 13 Get Left/Right 0: Right amplifier gain is requested 1: Left amplifier gain is requested 12:4 Reserved. Read as 0's 3:0 Index[3:0] for Input Source Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for 02h (FRONT DAC), 03h (SURR DAC), 04h (CEN/LFE DAC) Bit Description www..com 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Read as 0. (No Input Amplifier Mute) Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0. (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from -64B~0dB in 1dB steps
Codec Response for 08h (ADC) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -13.5B~+33dB in 1.5dB steps Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute)
Codec Response for 09h (ADC) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -13.5B~+33dB in 1.5dB steps Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute) Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index) Bit-15 is 1 in `Get Amplifier Gain': Read as 0. (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~31) specifying the volume from -34.5dB~+12dB in 1.5dB steps Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute)
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Codec Response for NID=0Ch~0Eh (Sum Widget: Front, Surr, Cen/Lfe) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response for NID=14h, 15h, 16h and 1Ah (Pin Widget: FRONT/SURR/CEN/LINE1) Bit Description 31:8 0's www..com 7 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Mute) Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Mute, 0:Unmute, 1:Mute (Default=1) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response for NID=18h, 19h and 1Bh (Pin Widget: MIC1/MIC2/LINE2) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Mute) Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Mute, 0:Unmute, 1:Mute (Default=1) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0] specifying the boost from 0dB/10dB/20dB/30dB in 10dB per step. (Default=0, 0dB) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response for NID=22h (Sum Widget) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute (Default=1 for all index) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response for NID=23h (Sum Widget) Bit Description 31:8 0's 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute (Default=1 for all index) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain)
Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.12. Verb - Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 47. Verb - Set Amplifier Gain (Verb ID=3h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=3h Payload Bit [7:0] `Set' payload [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Set' Payload in Command Bit[15:0] Bit Description www..com 15 Set Output Amp 1: Indicates output amplifier gain will be set 14 Set Input Amp 1: Indicates input amplifier gain will be set 13 Set Left Amp 1: Indicates left amplifier gain will be set 12 Set Right Amp 1: Indicates right amplifier gain will be set 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets) 5-bit index offset in connection list is used to select the input gain that will be set on a Sum or a Selector widget. The index is ignored if the node is not a Sum or a Selector widget, or the `Set Input Amp' bit is not set 7 Mute 0: Unmute 1: Mute (- gain) 6:0 Gain[6:0] A 7-bit step value specifying the amplifier gain
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8.13. Verb - Get Converter Format (Verb ID=Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 48. Verb - Get Converter Format (Verb ID=Ah) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Ah 0's Bit[15:0] are converter format
Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC, and S/PDIF-OUT). Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h) Bit Description 31:16 Reserved. Read as 0 www..com 15 Stream Type (TYPE) 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE) 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT) 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved 10:8 Sample Base Rate Divisor (DIV) 000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 Not supported. Always read as 000b 7 Reserved. Read as 0 6:4 Bits per Sample (BITS) 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved 3:0 Number of Channels. 0: 1 channel 1: 2 channels 2: 3 channels ..... 15: 16 channels
NID=02h (Front DAC) NID=03h (Surr DAC) NID=04h (Cen/Lfe DAC) NID=06h (S/PDIF-OUT) NID=08h (ADC) NID=09h (ADC)
Table 49. BASE 0 1 0 1 0 1 0 1 0 1 0 1
Get Converter Format Support MULT DIV BITS 000b,001b 000b 001,010b, 011b 000b 000b 001,010b, 011b 000b,001b 000b 001,010b, 011b 000b 000b 001,010b, 011b 000b,001b 000b 001,010b, 011b 000b 000b 001,010b, 011b 000b,001b 000b 001,010b, 011b 000b 000b 001,010b, 011b 000b,001b 000b 001b,010b, 000b 000b 001b,010b, 000b,001b 000b 001b,010b, 000b 000b 001b,010b,
Sample Rate 48K, 96K 44.1K 48K, 96K 44.1K 48K, 96K 44.1K 48K, 96K 44.1K 48K, 96K 44.1K 48K, 96K 44.1K
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.14. Verb - Set Converter Format (Verb ID=2h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 50. Verb - Set Converter Format (Verb ID=2h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=2h Set format [15:0] 0's for all nodes
`Set' Payload in Command Bit[15:0] Bit Description 31:16 Reserved. Read as 0 15 Stream Type (TYPE) www..com 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE) 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT) 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved 10:8 Sample Base Rate Divisor (DIV) 000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 7 Reserved. Read as 0 6:4 Bits per Sample (BITS) 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved 3:0 Number of Channels 0: 1 channel 1: 2 channels 2: 3 channels ........ 15: 16 channels
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8.15. Verb - Get Power State (Verb ID=F05h)
Table 51. Verb - Get Power State (Verb ID=F05h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID= F05h Payload Bit [7:0] 0's Codec Response Format Response [31:0] Power State [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:6 Reserved. Read as 0's. 5:4 PS-Act. Actual Power State [1:0]. www..com 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes (NID=01h), PS-Act is always equal to PS-Set. 3:2 Reserved. Read as 0's. 1:0 PS-Set. Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Set controls the current power setting of the referenced node.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.16. Verb - Set Power State (Verb ID=705h)
Table 52. Verb - Set Power State (Verb ID=705h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=705h Payload Bit [7:0] Power State [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Power State' in Command Bit[7:0] Bit Description 7:6 Reserved. Read as 0's 5:4 PS-Act. Actual Power State [1:0] www..com 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node 3:2 Reserved. Read as 0's 1:0 PS-Set. Set Power State [1:0] 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
8.17. Verb - Get Converter Stream, Channel (Verb ID=F06h)
Table 53. Verb - Get Converter Stream, Channel (Verb ID=F06h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F06h 0's Stream & Channel [7:0]
Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC and S/PDIF-OUT) Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h) Bit Description 31:8 Reserved. Read as 0's 7:4 Stream[3:0] The link stream used by the converter. 0000b is unused, 0001b is stream 1, etc. 3:0 Channel[3:0] The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.18. Verb - Set Converter Stream, Channel (Verb ID=706h)
Table 54. Verb - Set Converter Stream, Channel (Verb ID=706h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0's for all nodes
`Stream and Channel' in Command Bit[7:0] Bit Description 31:8 Reserved. Read as 0's 7:4 Set Stream[3:0] www..com The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 1:0 Set Channel[3:0] The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel
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8.19. Verb - Get Pin Widget Control (Verb ID=F07h)
Table 55. Verb - Get Pin Widget Control (Verb ID=F07h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F07h 0's Pin Control [7:0]
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT) Bit Description 31:8 Reserved. Read as 0's www..com 7 H-Phn Enable 0: Disabled 1: Enabled Note: Only NID=14h(FRONT), 19h(MIC2) and 1Bh(LINE2) support headphone amplifier. 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit) 0: Disabled 1: Enabled Note: NID=1Ch(CD-IN) and 1Dh(PCBEEP) do not support output and are always read 0. 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit) 0: Disabled 1: Enabled Note: NID=1Eh(S/PDIF-OUT) does not support output and is always read 0. 4:3 Reserved 2:0 VrefEn (Vrefout Enable Control) 000b: Hi-Z (Disabled, default for all) 001b: 50% of AVDD (ALC662 supports 2.5V reference output when AVDD is 5V) 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD (ALC662 supports 3.2V reference output when AVDD is 5V) 101b: 100% of AVDD 110b~111b: Reserved Note: Only NID=18h, 19h and 1Bh support reference output, other nodes will ignore this verb and respond with 0.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
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8.20. Verb - Set Pin Widget Control (Verb ID=707h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 56. Verb - Set Pin Widget Control (Verb ID=707h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=707h Pin Control [7:0] 0's for all nodes
`Pin Control' in command [7:0]: (NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh) (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT) Bit Description 31:8 Reserved. Read as 0's www..com 7 H-Phn Enable 0: Disabled 1: Enabled Note: Only NID=14h(FRONT), 19h(MIC2) and 1Bh(LINE2) support headphone amplifier. 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit) 0: Disabled 1: Enabled Note: NID=1Ch(CD-IN) and 1Dh(PCBEEP) do not support output and are always read 0. 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit) 0: Disabled 1: Enabled Note: NID=1Eh(S/PDIF-OUT) does not support output and is always read 0. 4:3 Reserved 2:0 VrefEn (Vrefout Enable Control) 000b: Hi-Z (Disabled, default for all) 001b: 50% of AVDD 010b: Ground 0V 011b: Reserved 100b: 80% of AVDD 101b: 100% of AVDD 110b~111b: Reserved Note: Only NID=18h, 19h, and 1Bh support reference output. Other nodes will ignore this verb and respond with 0.
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8.21. Verb - Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an unsolicited response to inform software of a real time event.
Table 57. Verb - Get Unsolicited Response Control (Verb ID=F08h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F08h 0's 32-bit Response
Codec Response www..com Bit 31:8 7 6:4 3:0
for NID=01h (GPIO), 14h~16h, 18h~1Bh (Port jack detection) Description Reserved. Read as 0's Unsolicited Response is Enabled 0: Disabled 1: Enabled Reserved. Read as 0's Assigned Tag for Unsolicited Response The tag[3:0] is assigned by software to determine which widget generates unsolicited responses
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
8.22. Verb - Set Unsolicited Response Control (Verb ID=708h)
Enable a widget to generate an unsolicited response.
Table 58. Verb - Set Unsolicited Response Control (Verb ID=708h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0's for all nodes
`EnableUnsol' in Command Bit [7:0] Bit Description 31:8 Reserved. Read as 0's 7 Unsolicited Response 0: Disable 1: Enable 6 Reserved. Read as 0's 5:0 Tag for Unsolicited Responses. Tag[5:0] is defined by software to assign a 6-bit tag for nodes that are enabled to generate unsolicited responses.
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8.23. Verb - Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 59. Verb - Get Pin Sense (Verb ID=F09h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID= F09h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2) www..com Bit Description 31 Presence Detect Status 0: No device is attached to the pin 1: Device is attached to the pin 30:0 Measured Impedance The ALC662 does not support hardware impedance detect. This field is read as 0s.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h)
8.24. Verb - Execute Pin Sense (Verb ID=709h)
Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 60. Verb - Execute Pin Sense (Verb ID=709h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID= 709h Right Channel[0] 0's for all nodes
`Payload' in Command Bit[7:0] (for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh) Bit Description 7:1 Reserved. Read as 0's 0 Right (Ring) Channel Select 0: Sense Left channel (Tip) 1: Sense Right channel (Ring) The ALC662 does not support hardware impedance detect and will ignore this control bit.
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8.25. Verb - Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)
Read the 32-bit sticky register for each Pin Widget configured by software.
Table 61. Verb - Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F1Ch 0's 32-bit Response
www..com
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh (Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, S/PDIF-OUT) Bit Description 31:0 32-bit configuration information for each pin widget Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function Reset Verb).
8.26. Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions (e.g., placement and expected default device) for the Pin Widgets NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h.
Table 62. Verb - Set Configuration Default Bytes 0, 1, 2, 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=71Ch, Label [7:0] 0's for all nodes 71Dh, 71Eh, 71Fh Note: Supported by Pin Widget NID=14h~16h, 18h~1Bh, 1Ch, 1Dh, and 1Eh. Other widgets will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's
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8.27. Verb - Get BEEP Generator (Verb ID=F0Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Table 63. Verb - Get BEEP Generator (Verb ID= F0Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID= F1Bh 0's Divider [7:0]
`Response' for NID=01h Bit Description 31:8 Reserved 7:0 Frequency Divider, F[7:0] www..com The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0] The lowest tone is 48kHz/(255*4)=47Hz The highest tone is 48kHz/(1*4)=12kHz A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input
Codec Response for Other NID Bit Description 31:0 0's
8.28. Verb - Set BEEP Generator (Verb ID=70Ah)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Table 64. Verb - Set BEEP Generator (Verb ID= 70Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=71Bh Divider [7:0] 0's for all nodes
`Divider' in Set Command Bit Description 31:8 Reserved 7:0 Frequency Divider, F[7:0] The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0] The lowest tone is 48kHz/(255*4)=47Hz The highest tone is 48kHz/(1*4)=12kHz A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input Note: All nodes except BEEP generator (NID=01h) will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's
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8.29. Verb - Get GPIO Data (Verb ID= F15h)
Table 65. Verb - Get GPIO Data (Verb ID= F15h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Bit [19:8] Verb ID=F15h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved www..com 1:0 GPIO[1:0] Data The value written (output) or sensed (input) on the corresponding pin if it is enabled
Codec Response for Other NID Bit Description 31:0 0's
8.30. Verb - Set GPIO Data (Verb ID= 715h)
Table 66. Verb - Set GPIO Data (Verb ID= 715h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Bit [19:8] Verb ID=715h Payload Bit [7:0] Data [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Data' in Set command for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved 1:0 GPIO[1:0] Output Data The value written determines the value driven on a pin that is configured as an output pin
Codec Response for All NID Bit Description 31:0 0's
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8.31. Verb - Get GPIO Enable Mask (Verb ID=F16h)
Table 67. Verb - Get GPIO Enable Mask (Verb ID= F16h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=F16h 0's EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved www..com 1:0 GPIO[1:0] Enable mask 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID Bit Description 31:0 0's
8.32. Verb - Set GPIO Enable Mask (Verb ID=716h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Table 68. Verb - Set GPIO Enable Mask (Verb ID=716h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=716h Enable Mask [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved 1:0 GPIO[1:0] Enable Mask 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's
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8.33. Verb - Get GPIO Direction (Verb ID=F17h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Table 69. Verb - Get GPIO Direction (Verb ID=F17h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F17h 0's Direction [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved www..com 1:0 GPIO[1:0] Direction Control 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for Other NID Bit Description 31:0 0's
8.34. Verb - Set GPIO Direction (Verb ID=717h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=01h Table 70. Verb - Set GPIO Direction (Verb ID=717h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=717h Direction [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved 1:0 GPIO[1:0] Direction Control 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID Bit Description 31:0 0's
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8.35. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Table 71. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=F19h 0's UnsolEnable [7:0] Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved www..com 7:2 Reserved 1:0 GPIO[1:0] Unsolicited Enable mask 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for Other NID Bit Description 31:0 0's
8.36. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Table 72. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=719h UnsolEnable [7:0] 0's for all nodes Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved 7:2 Reserved 1:0 GPIO[1:0] Unsolicited Enable Mask 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb. Note 2: The unsolicited response of corresponding GPIO is enabled when it's `Enable Mask' and Verb-`Unsolicited Response' for NID=01h are enabled. Codec Response for Other NID Bit Description 31:0 0's
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8.37. Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Table 73. Verb - Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=06h Verb ID=F0Dh/ 0's Bit[31:16]=0's, Bit[15:0] are SIC bit F0Eh
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NID=06h (S/PDIF-OUT Converter) Response to `Get verb' - F0Dh (Control for SIC bit[15:0]) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 31:16 Read as 0's 15 Reserved. Read as 0's 14:8 CC[6:0] (Category Code) 7 LEVEL (Generation Level) 6 PRO (Professional or Consumer format) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright) 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis) 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame) 1 V for Validity Control (control V bit and data in Sub-Frame) 0 Digital Enable. DigEn 0: OFF 1: ON
Codec Response for Other NID Bit Description 31:0 0's
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8.38. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Table 74. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) Set Command Format (Verb ID=70Dh, Set Control 1) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=06h Verb ID=70Dh SIC [7:0] 0's
Set Command Format (Verb ID=70Eh, Set Control 2) Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] www..com CAd=X Node ID=06h Verb ID=70Eh SIC [15:8]
Codec Response Format Response [31:0] 0's
`Payload' in Set Control 1 for NID=06h (S/PDIF-OUT Converter) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7 LEVEL (Generation Level) 6 PRO (Professional or Consumer format) 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type) 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright) 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis) 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame) 1 V for Validity Control (control V bit and data in Sub-Frame) 0 Digital Enable. DigEn 0: OFF 1: ON
`Payload' in Set Control 2 for NID=06h (S/PDIF-OUT Converter) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0's 6:0 CC[6:0] (Category Code)
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8.39. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 75. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=F20h 0s 32-bit Response
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Codec Response for NID=01h Bit Description 31:16 Subsystem ID[23:8]. (Default=10ECh) 15:8 Subsystem ID[7:0]. (Default=06h) 7:0 Assembly ID[7:0]. (Default=62h)
8.40. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 76. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0]) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=723h, Label [7:0] 0s for all nodes 722h, 721h, 720h
Codec Response for all NID Bit Description 0s 31:0
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8.41. Verb - Get/Set EAPD Control (Verb ID=F0Ch for Get, 70Ch for Set)
Table 77. Verb - Get EAPD Control (Verb ID=F0Ch) Get Command Format (NID=14h and 15h) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node Verb ID=F0Ch 0s Bit[1] is EAPD Control ID=14h/15h Codec Response for NID=14h (FRONT, port-D) and 15h (SURR, port-A) Bit Description www..com 31:3 Reserved 2 L-R Swap The ALC662 does not support swapping left and right channels. Read as 0. 1 EAPD Value 0: EAPD pin state is low 1: EAPD pin state is high 0 BTL Enable The ALC662 does not support BTL output. Read as 0. Codec Response for Other NID Bit Description 31:0 0's
Table 78. Verb - Set EAPD Control (Verb ID=70Ch) Set Command Format (NID=14h and 15h) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node Verb ID=70Ch Bit[1] is EAPD Control 0s ID=14h/15h
Payload in Set command for NID=14h (FRONT, port-D) and 15h (SURR, port-A) Bit Description 31:3 Reserved 2 L-R Swap The ALC662 does not support swapping left and right channels. Read as 0. 1 EAPD Value 0: EAPD pin state is low 1: EAPD pin state is high. Note: Only one physical logic for the EAPD signal. 0 BTL Enable The ALC662 does not support BTL output. Read as 0. Codec Response Bit Description 31:0 0's
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8.42. Verb - Function Reset (Verb ID=7FFh)
Table 79. Verb - Function Reset (Verb ID=7FFh) Command Format (NID=01h) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=7FFh 0's 0's
Codec Response Bit Description 31:0 Reserved. Read as 0's Note: The www..com Function Reset command causes all widgets to return to their power-on default state.
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9.
9.1.1.
Electrical Characteristics
Absolute Maximum Ratings
Table 80. Absolute Maximum Ratings Symbol Minimum Typical DVDD DVDD-IO* AVDD** Ta Ts 2.7 1.5 3.0 0 3.3 3.3 5.0 Maximum 3.6 3.6 5.5 +70 Units V V V o C
9.1. DC Characteristics
Parameter Power Supply: Digital power for core Digital power for HDA link www..com Analog Ambient Operating Temperature Storage Temperature
o +125 C ESD (Electrostatic Discharge) Susceptibility Voltage Digital pins 3500V Analog pins 4000V Note*: The digital link power DVDD-IO must be lower than the digital core power DVDD. Note** : The standard testing condition before shipping is AVDD = 5.0V unless specified. Customers designing with a different AVDD should contact Realtek technical support representatives for special testing support..
9.1.2.
Threshold Voltage
Table 81. Threshold Voltage Symbol Minimum Typical Vin -0.30 VIL VIH VIL VIH VOH VOL 0.65* DVDDIO 0.56* DVDD (1.85) 0.9*DVDD -10 -10 5 50k
DVDD=3.3V5%, Tambient=25C, with 50pF external load.
Parameter Input Voltage Range Low Level Input Voltage (HDA link) High Level Input Voltage (HDA link) Low Level Input Voltage (S/PDIF-OUT) High Level Input Voltage (S/PDIF-OUT) High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current (Hi-Z) Output Buffer Drive Current Internal Pull Up Resistance Maximum DVDD +0.30 0.30* DVDDIO 0.44*DVDD (1.45) 0.1*DVDD 10 10 100k Units V V V V V V V A A mA
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9.1.3.
S/PDIF Output Characteristics
Table 82. S/PDIF Output Characteristics Symbol Minimum Typical VOH 3.0 3.3 VOL 0
DVDD= 3.3V, Tambient=25C, with 75 external load.
Parameter S/PDIF-OUT High Level Output S/PDIF-OUT Low Level Output Maximum 0.3 Units V V
9.2. AC Characteristics
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9.2.1.
Link Reset and Initialization Timing
Maximum 1 Units s s Frame Time
Table 83. Link Reset and Initialization Timing Parameter Symbol Minimum Typical RESET# Active Low Pulse Width TRST 1.0 RESET# Inactive to BCLK TPLL 20 Startup delay for PLL ready time SDI Initialization Request TFRAME -
4 BCLK
4 BCLK
>= 4 BCLK
Initialization Sequence
BCLK SYNC SDO SDI
Initialization Request Normal Frame SYNC
RESET#
TRST TPLL T FRAME
Figure 14. Link Reset and Initialization Timing
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9.2.2.
Link Timing Parameters at the Codec
Units MHz ns ns ns (%) ns (%) ns ns ns ns
Table 84. Link Timing Parameters at the Codec Symbol Minimum Typical Maximum 24.0 Tcycle 41.67 Tjitter 2.0 Thigh 18.75 22.91 (45%) (55%) BCLK Low Pulse Width Tlow 18.75 22.91 (45%) (55%) SDO Setup Time at Both Rising Tsetup 2.1 and Falling Edge of BCLK www..com SDO Hold Time at Both Rising and Thold 2.1 Falling Edge of BCLK SDI Valid Time After Rising Edge Ttco 7.5 8.0 of BCLK (1: 50pF external load) SDI Flight Time Tflight 2.0 Parameter BCLK Frequency BCLK Period BCLK Jitter BCLK High Pulse Width
T _ c y c le T _ h ig h
BCLK
V IH VT V IL T _ s e tu p T _ h o ld T _ lo w
SDO
T _ tc o VO H
SDI
VO L T _ flig h t
Figure 15. Link Signal Timing
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9.2.3.
S/PDIF Output Timing
Table 85. S/PDIF Output Timing Symbol Minimum Typical 3.072 Tcycle 325.6 Tjitter THigh 156.2 (48%) 162.8 (50%) TLow 156.2 (48%) 162.8 (50%) Trise 2.0 Tfall 2.0 Maximum 4 169.2 (52%) 169.2 (52%) Units MHz ns ns ns (%) ns (%) ns ns
Parameter S/PDIF-OUT Frequency S/PDIF-OUT Period S/PDIF-OUT Jitter S/PDIF-OUT High Level Width S/PDIF-OUT Low Level Width S/PDIF-OUT Rising Time S/PDIF-OUT Falling Time
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T c y c le T h ig h V IH V IL T r is e T f a ll
Figure 16. Output Timing
T lo w
VOH Vt V OL
9.2.4.
Test Mode
Codec test mode and Automatic Test Equipment (ATE) mode are not supported.
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9.3. Analog Performance
Standard Test Conditions * * * Tambient=25 oC, DVDD= 3.3V 5%, AVDD=5.0V5% 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms 10K/50pF load; Test bench Characterization BW: 10Hz~22kHz
Max > 20,000 > 20,000 +0.20 -90 / -80 110 0.2 2 3.2 Units Vrms Vrms Vrms dB FSA dB FSA dBFS A dB FS dB FS dB FS Hz Hz dB dB dB dB dB Degree K mA mA V mA
Table 86. Analog Performance Parameter Min Typ Full Scale Input Voltage All Inputs (gain=0dB) 1.6 www..com All ADC 1.4 Full Scale Output Voltage All DAC 1.4 S/N (A Weighted) All ADC 90 All DAC 98 Headphone Amplifier 98 THD+N ADC -85 All DAC -92 -75 Headphone Amplifier (32 Load) Magnitude Response ADC (-3dB lower edge, -1dB higher edge)*1 0 DAC (-3dB lower edge, -1dB higher edge)*1 0 Pass band ripple for DAC and ADC -0.20 Power Supply Rejection Ratio -40 Total Out-of-Band Noise (28.8kHz~100kHz) -60 Crosstalk Between Output Channel (1kHz / 20kHz) Output Noise Level During System Activity Output Inter-Channel Phase Delay Input Impedance (gain=0dB) 40 Output Impedance Line Output 100 Amplified Output 1 Power Supply Current (normal operation) AVDD=5V / DVDD=3.3V 38 / 23 Power Supply Current (power down mode) AVDD=5V / DVDD=3.3V 0.4 / 1.1 VREFOUTx Output Voltage (AVDD=5.0V) 2.5 VREFOUTx Output Current (AVDD=5.0V) 5 *1: The higher edge of magnitudes for DAC and ADC are -0.6dB@20,000Hz
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10. Application Circuits
The ALC662 is fully pin to pin compatible with the ALC660 and the ALC88x series. Please contact Realtek to get the latest application circuits. To get the best compatibility in hardware design and software driver, any modifications should be confirmed by Realtek. Realtek may update the latest application circuits onto our web site (www.realtek.com.tw) without modifying this data sheet.
10.1. Filter Connection
Front panel header option-2 Resistors placed www..com beside onboad front panel header
LINE2-JD MIC2-JD MIC1-VREFOR LINE2-VREFO MIC2-VREFO MIC1-VREFOL +5VA
Front panel header option-1
FRONT-IO-JD FRONT-IO-JD
R2 is for SIDE Output not required for ALC662 R2
CEN-JD R3
5.1K,1% (NC) 10K,1%
FRONT-L FRONT-R C17 10u + 35 34 33 32 31 30 29 28 27 26 25 AVSS1 NC NC VREF FRONT-L Sense B LINE2-VREFO MIC2-VREFO FRONT-R MIC1-VREFO-R MIC1-VREFO-L AVDD1 LINE1-R LINE1-L MIC1-R MIC1-L CD-R CD-GND + C18 10u
+5VA
36
U2
C21 10u
+
37 38 SURR-L 39 40
NC AVDD2 SURR-L JDREF SURR-R AVSS2 CENTER LFE NC NC EAPD
24 23 22 21 20 19 18 17 16 15 14 13 C26 C29 C32 1u 1u 1u
LINE1-R LINE1-L MIC1-R MIC1-L 4 3 2 1 J1
R6
SURR-R
41 42
20K,1%
CEN LFE SIDESURR-L SIDESURR-R EAPD
43 44 45 46 47 48
ALC662
CD-L MIC2-R MIC2-L LINE2-R LINE2-L
MIC2-R MIC2-L LINE2-R LINE2-L R7 R8 R9 R10
CD-IN Header
SDATA-OUT
SDATA-IN
SPDIFO GPIO0 GPIO1 DVDD DVSS
Sense A DVDD-IO PCBEEP RESET# SYNC
5.1K,1% FRONT-JD 10K,1% 20K,1%
LINE1-JD MIC1-JD
FRONT-JD LINE1-JD MIC1-JD SURR-JD
BIT-CLK
S/PDIF-OUT
DVSS
10
11
+3.3VD C34 + 10u R16 22
12
39.2K,1% SURR-JD
1
2
3
4
5
6
7
8
9
C33
1u C36 100P
R13
10K Ext. PCBEEP
RESET# SYNC SDIN
R15 1K
GPIO0 GPIO1 R17 C40 22P 22
BCLK
DGND
SDOUT
AGND
Tied at one point only under the codec or near the codec
Figure 17. Filter Connection
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10.2. Onboard Front Panel Header Connection and Front Panel I/O
Option 1: Follow Intel's HD Audio front panle header design (Two ports must be in the same jack detect group)
MIC2-VREFO D3 1N4148 R11 D4 1N4148 R12 4.7K R14 MIC2-L MIC2-R LINE2-R LINE2-L C35 C37 C38 C39 1u 1u 100u FRONT-IO-JD 100u + J3 1 3 5 7 9 CON10A 2 4 6 8 10 MIC2-JD PRESENCE# System GPI FIO-SENSE LINE2-JD R19 R18 JACK 7 FIO-PORT2-R FIO-PORT2-L L14 L15 FERB FERB C41 C42 100P FIO-PORT2 (Jack-E) PORT2-SENSE-RETURN 4 3 5 2 1 10K +3.3VD FIO-PORT1-L FIO-PORT1-R FIO-PORT2-R FIO-SENSE FIO-PORT2-L
HD Audio Front Panel I/O Cable
J2 1 3 5 7 9 CON10A 2 4 6 8 10 FIO-PRESENCE# PORT1-SENSE-RETURN
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4.7K
KEY
PORT2-SENSE-RETURN
+
Key
Onboard front panel header
39.2K,1%
20K,1%
Option 2: A more flexible front panel header (Each port can be in different jack detect group)
MIC2-VREFO D5 1N4148 R20 4.7K MIC2-L MIC2-R LINE2-R LINE2-L C44 C46 C48 C51 1u 1u 100u 100u J5 1 3 5 7 9 CON10A 2 4 6 8 10 R25 Key R26 D6 1N4148 R21 4.7K R23 10K PRESENCE# System GPI FIO-PORT1-R FIO-PORT1-L L16 L17 +3.3VD
100P
FIO-SENSE JACK 8 PORT1-SENSE-RETURN FERB FERB C49 C50 FIO-PORT1 (Jack-F) 100P 100P 4 3 5 2 1
20K,1%
MIC2-JD LINE2-JD
+
Sense B Sense B
+
Onboard front panel header
39.2K,1%
Figure 18. Onboard Front Panel Header Connection and Front Panel I/O
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10.3. Analog Input/Output Connection
JACK 2 FRONT-JD FRONT-R FRONT-L C1 C3 100u 100u L1 L3 FERB FERB C5 C6 + JACK 1 4 3 5 2 1 FRONT-OUT SURR-R SURR-L C2 C4 1u 1u L2 L4 FERB FERB C7 100P C8 100P SURR-OUT SURR-JD 4 3 5 2 1
+
100P 100P
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LINE1-R LINE1-L
LINE1-JD C9 C11 1u 1u L6 L8 FERB FERB C15 C16
JACK 3 4 3 5 2 1 LINE-IN C19 100P C20 100P CEN-JD LFE CEN C10 C14 1u 1u L7 L9 FERB FERB
JACK 4 4 3 5 2 1 CEN/LFE-OUT
100P 100P MIC1-VREFO-L MIC1-VREFO-R
R4 4.7K MIC1-R MIC1-L C22 C24 1u 1u
R5 4.7K L10 L12 FERB FERB C27 C28 MIC1-JD 4 3 5 2 1 JACK 5 MIC-IN
100P 100P
Figure 19. Analog Input/Output Connection
10.4. Optional S/PDIF Output
S/PDIF module option 1: Optical
U3
S/PDIF module option 2: Coaxial
TOTX178
5 N.C GND VCC
Optical Transmitter
N.C 4 J4 IN 1 C45 100P 2 R22 200 C43 S/PDIF-OUT 0.01u
S/PDIF OUTPUT (Coaxial)
S/PDIF-OUT
R24 100
1
2
+5VD
C47 0.1u
3
Figure 20. Optional S/PDIF Output
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11. Mechanical Dimensions
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L L1
See the Mechanical Dimensions notes on the next page.
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11.1. Mechanical Dimensions Notes
SYMBOL
A A1 A2 c D www..com D1 D2 E E1 E2 b e TH L L1
MILLIMETER MIN. TYP MAX. 1.60 0.05 0.15 1.35 1.40 1.45 0.09 0.20 9.00 BSC 7.00 BSC 5.50 9.00 BSC 7.00BSC 5.50 0.17 0.20 0.27 0.50 BSC o 0 3.5o 7o 0.45 0.60 0.75 1.00
INCH TYP MAX 0.063 0.002 0.006 0.053 0.055 0.057 0.004 0.008 0.354 BSC 0.276 BSC 0.217 0.354 BSC 0.276 BSC 0.217 0.007 0.008 0.011 0.0196 BSC o 0 3.5o 7o 0.018 0.0236 0.030 0.0393 MIN.
TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION 02 CHECK DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP.
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12. Ordering Information
Table 87. Ordering Information Part Number Package Status ALC662-GR LQFP-48 `Green' package Sample Note 1: See page 4 for Green package and version identification. Note 2: Above parts are tested under AVDD=5.0V. If customers have lower AVDD request, please contact Realtek sales representatives or agents.
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Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-557-6047 www.realtek.com.tw
5.1 Channel High Definition Audio Codec 71 Rev. 1.0

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